Flash memories and other similar non-volatile memories store data in a memory cell by programming the threshold voltage of a transistor (e.g., a floating gate transistor) in the memory cell to a level that corresponds to the data being stored. For example, storing a single bit of data in this type of memory cell requires erase and programming operations that can consistently set the threshold voltages of transistors to either of two different threshold voltage levels that can be distinguished without errors during read operations. Storing N bits in a memory generally requires programming that can set a transistor in any of 2N or (2N−1) different threshold voltage levels that can be distinguished from each other without error during subsequent read operations. Since the structure and operating voltage of memory cells limit the available range of useable threshold voltages, programming operations become exponentially more difficult as the number of bits stored per memory cell increases.
A primary difficulty when storing four or more bits of data in a Flash memory cell is the unavoidable variation in the programming characteristics or performance of the memory cells. In particular, known programming mechanisms including Channel Hot Electron (CHE) injection and Fowler-Nordheim (FN) tunneling will be more efficient in some memory cells in a memory array causing faster programming (e.g., faster threshold voltage changes) of some “fast” memory cells. On the other hand, some memory cells in the same memory array will be less efficient causing slower programming (e.g., slower threshold voltage changes) of some “slow” memory cells. The variations in programming characteristics or performance are difficult or impossible to eliminate because the variations arise from a variety of factors and effects. Variations during manufacturing processes across a wafer and across wafers in a wafer lot, and differences in the location of memory cells within a memory array or within an integrated circuit, for example, can cause the memory cells to perform differently. Further, even if two memory cells had identical programming performance when new, different use of the memory cells, e.g., storage of different data values or being subject to differing numbers of programming and erase operations, can change the memory cells over time so that the two memory cells no longer have the same programming characteristics.
Another difficulty for programming operations is achieving a high data I/O rate. A programming operation designed to program a fast memory cell with the required threshold voltage accuracy for four or more bits per memory cell (≥4 bpc) may require an unacceptably long time for programming of slow memory cells. In such cases, the slow memory cells could be indicated as defective, causing low manufacturing yield and/or short product life, or the poor performance of the slow memory cells limit the data I/O rate of the memory during writing. Alternatively, a programming operation designed for slow-programming memory cells (e.g., programming operations using higher applied programming voltages) may cause rapid changes in the threshold voltages of fast memory cells, resulting in inaccurate programming of the fast memory cells. Circuits and methods for quickly and accurately programming both fast and slow nonvolatile memory cells within a memory array or an integrated circuit are therefore desired.
Read operations for multi-bit-per-cell memory need to accurately measure or quantify a memory cell's threshold voltage in order to determine the multi-bit data stored. However, the size of each threshold voltage window representing a data value decreases by a factor (2N−1), where N is the number of bits stored in the memory cell. The reduced threshold voltage window size would reduce the sensing margin, i.e., the threshold voltage difference between the selected memory cell and reference cell. Differentiating such a small delta signal requires a highly-sensitive sense amplifier with memory and reference cell data paths that are well balanced in terms of capacitive, resistive, noise, and coupling effects. In order to maximize the delta signal read out from the memory and reference cells, it is important to bias both cells in an operating region where changes in current flow is most sensitive to changes in threshold voltage. Furthermore, Flash memories with random access feature require high speed reading of a number of memory cells in less than about 100 ns, which further challenges the read operation. Therefore, circuits and methods for quickly and accurately reading multi-bit-per-cell nonvolatile memories are desired.